The present invention generally relates to a semiconductor device and, more particularly, to a semiconductor device formed as a gate array having a large number of logic cells on a chip.
This device offers great logic flexibility and is therefore receiving a lot of attention. A gate array is used for replacing IC packages on a circuit board with a single LSI circuit. A gate array generally has basic cells, i.e., NAND gates or NOR gates, which are regularly arranged on a chip. These gates may be connected to build any logic function. By interconnecting gates as flip-flops, adders, multiplexers, etc., these circuit elements can be placed in any combination anywhere on a chip. Thus, a circuit designer need only interconnect the gates with a dedicated metal pattern in order to form a custom-circuit logic function. Since various types of LSIs can be manufactured from gate arrays of the same specifications, utilization of gate arrays results in savings in development time and cost.
Conventionally, a custom-circuit LSI based on a gate array cannot have a large capacity memory. This is attributed to the following reason. Since memories such as general registers, floating registers or the like require many arrayed gates, the number of gates for forming circuit elements other than the memory becomes small. Furthermore, a memory obtained by a combination of arrayed gates has a slow operating speed.